Non-binary LDPC decoder using binary subgroup processing

ABSTRACT

In one embodiment, an electronic system includes a decoder configured to decode an encoded data unit using multiple variable nodes and multiple check nodes to perform a low-density parity check (LDPC) decoding process. The encoded data unit can be received from a solid-state memory array. As part of performing the LDPC decoding process, the decoder can (i) convert reliability information representing first non-binary values to reliability information representing first binary values, (ii) determine reliability information representing second binary values using the reliability information representing first binary values, and (iii) convert the reliability information representing the second binary values to reliability information representing second non-binary values.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims benefit under 35 U.S.C. §119(e) to U.S. Provisional Patent Application No. 61/933,147 entitled “NON-BINARY LDPC DECODER USING BINARY SUBGROUP PROCESSING” filed on Jan. 29, 2014; the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

1. Technical Field

This disclosure relates in part to data storage systems for computer systems. More particularly, the disclosure relates in part to a non-binary decoder using binary subgroup processing.

2. Description of the Related Art

Non-volatile memory arrays often have limited endurance. The endurance of the memory array is typically contingent on usage pattern and wear. In addition, the endurance depends on a type of the non-volatile memory array used. For example, memory arrays with multi-level cell (MLC) NAND media typically have a lower endurance than memory arrays with single-level cell (SLC) NAND media. To protect user data stored to memory arrays from corruption, which may be caused by a diminished endurance, user data can be encoded, for example, by generating parity data that can be stored along with user data to facilitate error detection and correction. However, decoding of encoded data can be time consuming and resource intensive. Accordingly, it is desirable to provide more efficient mechanisms for decoding data.

BRIEF DESCRIPTION OF THE DRAWINGS

Systems and methods disclosed herein will now be described with reference to the following drawings, in which:

FIG. 1A illustrates a combination of a host system and a data storage system that implements a non-binary decoder using binary subgroup processing according to one embodiment of the invention.

FIG. 1B illustrates a data transmission system according to one embodiment of the invention.

FIG. 2 illustrates a flow diagram depicting a decoding process by a decoder according to one embodiment of the invention.

FIGS. 3A and 3B illustrate a flow diagram depicting algorithms and data transfers in a decoding process by a decoder according to one embodiment of the invention.

FIGS. 4 and 5 are graphs illustrating the signal-to-noise ratio for given page error rates for decoders according to embodiments of the invention.

FIG. 6 illustrates a decoding process according to one embodiment of the invention.

DETAILED DESCRIPTION

While certain embodiments are described, these embodiments are presented by way of example only, and are not intended to limit the scope of protection. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the scope of protection.

Overview

Data storage systems, such as solid state drives, typically include one or more controllers coupled with one or more non-volatile memory arrays. Depending on the type of non-volatile memory array used, stored data may be subject to corruption as a result of, for example, read/write disturbs, loss of data retention, and/or loss of endurance. Data storage systems can utilize one or more error correction or error coding mechanisms to detect and/or correct errors in the stored data. One such mechanism can determine parity data when writing user data. Parity data can be stored, for example, in a memory array. When stored user data is retrieved, parity data can be utilized as part of a decoding process to determine the integrity of the retrieved user data. If one or more errors are detected, such errors may be corrected.

One type of error correction or error coding mechanism that can be used by data storage systems to code data is low-density parity-check (LDPC) codes. To manage LDPC coding, the data storage systems can include decoder and encoder modules that utilize the LDPC codes for decoding and generating parity data, respectively. The LDPC codes can be decoded using a decoding matrix H and generated using a corresponding generating matrix G. The decoding process performed by the decoder modules, in particular, can involve an iterative decoding process where values (for example, probabilities or likelihoods of belief) are passed between variable nodes and check nodes to decode data.

Data storage systems can implement LDPC coding to enable processing of binary and/or non-binary LDPC codes. In some embodiments, whether the data storage systems may decode or encode data using a binary LDPC code or non-binary LDPC code can, for example, depend on a number of memory states for a storage medium in which the data storage systems can store and retrieve data, whether multiple memory cells are grouped into a memory element, etc. For example, a data storage system can use binary LDPC codes for storing or retrieving data from one or more storage mediums including memory elements that store single bits of information, such as SLC NAND media which may store in a memory cell one of “0” and “1” values, and use non-binary LDPC codes for storing or retrieving data from one or more storage mediums including memory elements that store multiple bits of information, such as MLC NAND media or SLC NAND media in which two or more memory cells are grouped into a single memory element. For instance, two-level or two-bit MLC NAND can store in a memory cell one of “00,” “01,” “10,” and “11” values.

Embodiments of the present disclosure are directed in part to a LDPC decoder module that can decompose a non-binary decoding process into binary decoding processes. In one embodiment, the decomposition of the non-binary decoding processes into the binary decoding processes can enable the LDPC decoder module to arrive at the same decoding results as if the LDPC decoder module directly performed the decoding using the non-binary decoding process. In another embodiment, the decomposition of the non-binary decoding processes into the binary decoding processes can enable the LDPC decoder module to utilize simplifications or approximations to increase the speed at which the LDPC decoder module reaches decoding results. In yet another embodiment, the LDPC decoder module can utilize simplifications or approximations in the decoding process to remove logarithmic or exponential operations, reducing memory usage and implementation complexity for the LDPC decoder module. Advantageously, in certain embodiments, the decomposition of the non-binary decoding processes into the binary decoding processes can enable the LDPC decoder module perform the decoding process without evaluating numerous combinations of values to determine minimum values as may be done in some non-binary decoding processes, like in particular extended minimum-sum algorithms.

System Overview

FIG. 1 illustrates a combination 100A of a host system 110 and a data storage system 120 that implements a non-binary decoder using binary subgroup processing. As is shown, the data storage system 120 (e.g., hybrid hard drive, solid state drive, etc.) includes a controller 130 and a storage medium 140. The storage medium 140 may comprise an array of non-volatile memory, such as flash integrated circuits, Chalcogenide RAM (C-RAM), Phase Change Memory (PC-RAM or PRAM), Programmable Metallization Cell RAM (PMC-RAM or PMCm), Ovonic Unified Memory (OUM), Resistance RAM (RRAM), NAND memory (e.g., single-level cell (SLC) memory, multi-level cell (MLC) memory, or any combination thereof), NOR memory, EEPROM, Ferroelectric Memory (FeRAM), Magnetoresistive RAM (MRAM), other discrete NVM (non-volatile memory) chips, or any combination thereof. Non-volatile memory can be arranged in blocks having one or more pages, which comprise one or more memory cells. In some embodiments, the data storage system 120 can further comprise other types of storage, such as one or more magnetic media storage modules or other types of storage modules.

The controller 130 can be configured to receive data and/or storage access commands from a storage interface module 112 (e.g., a device driver) of the host system 110. Storage access commands communicated by the storage interface module 112 can include write data and read data commands issued by the host system 110. Read and write commands can specify a logical address (e.g., logical block addresses or LBAs) used to access the data storage system 120. The controller 130 can execute the received commands in the storage medium 140.

Data storage system 120 can store data communicated by the host system 110. In other words, the data storage system 120 can act as memory storage for the host system 110. To facilitate this function, the controller 130 can implement a logical interface. The logical interface can present to the host system 110 data storage system memory as a set of logical addresses (e.g., contiguous address) where user data can be stored. Internally, the controller 130 can map logical addresses to various physical locations or addresses in the storage medium 140 and/or other storage modules.

The controller 130 includes a decoder module 132 and an encoder module 134 configured to decode and encode data, respectively, stored in and retrieved from the storage medium 140. The encoder module 134 can encode stored data so as to, for example, protect the data from potential errors encountered during retrieval of stored data. The decoder module 132 can further perform error detection to determine the integrity of data retrieved from the storage medium 140 and perform, if necessary, error correction of retrieved data. In some embodiments, when the storage medium 140 comprises NAND memory that may be early in the lifecycle and thus have relatively higher retention and/or endurance, the controller 130 can direct the encoder module 134 to encode data using a relatively higher coding rate so that less parity data is used. As the storage medium 140 wears out over time, the controller 130 can direct the encoder module 134 to switch to lower encoding rates such that more parity data is generated to protect stored user data from errors. The controller 130 can store the coding rates for encoded data in the storage medium 140 or another storage module (not shown) so that the decoder module 132 can later access the information to decode the encoded data. In some embodiments, the decoder module 132 and the encoder module 134 can respectively decode LDPC coded data and encode data using LDPC codes.

FIG. 1B illustrates a data transmission system 100B according to one embodiment. In the data transmission system 100B, a transmitter 150 can send or transmit data to a receiver 158 over a data communication channel 154. The transmitted data can be encoded by an encoder 152 before the data is transmitted over the data communication channel 154. The data communication channel 154 can be any suitable wired and/or wireless connection, such as a satellite channel, 802.11 wireless channel, Ethernet channel, Bluetooth channel, connection between semiconductor components or devices, data storage device (e.g., magnetic, solid-state, or the like), and so on. The data transmitted over the data communication channel 154 can be decoded by a decoder 156. The decoded data can then be provided to the receiver 158.

LDPC Decoder

In some embodiments, the decoder module 132 can decode data that may have been encoded using a non-binary LDPC coding. The decoder module 132 can read retrieved data from the storage medium 140 and calculate log likelihood ratio (LLR) values (for example, vectors of LLR values) for one or more read channels based on the data. The decoder module 132 can then iteratively transfer LLR values between variable nodes and check nodes using one or more LDPC coding techniques to decode the data. The decoding process can iterate on average from 3 to 4 iterations and may complete after a predetermined maximum number of iterations, such as 20 iterations.

FIG. 2 illustrates a flow diagram 200 depicting a LDPC decoding process by a decoder, such as the decoder module 132 or the decoder 156. The flow diagram 200 illustrates the transfer of values from variable nodes 210A, 210B, 210C to binary check nodes 240A, 240B, 240C and back to the same variable nodes 210A, 210B, 210C. Conversion nodes 230A, 230B, 230C can facilitate the conversion of non-binary values from the variable nodes 210A, 210B, 210C to binary values for processing by the binary check nodes 240A, 240B, 240C. Inverse conversion node 250 can facilitate the conversion of binary values from the binary check nodes 240A, 240B, 240C to non-binary values for processing by the variable nodes 210A, 210B, 210C. The conversion nodes 230A, 230B, 230C, the binary check nodes 240A, 240B, 240C, and the inverse conversion node 250 can advantageously together operate as if to form a non-binary check node in certain embodiments. State transitions are represented by circled numbers in the flow diagram 200.

The example of flow diagram 200 demonstrates the decomposition of non-binary values for a Galois field of size four (i.e., GF(4)) at the variable nodes 210A, 210B, 210C. This example, however, is intended to be illustrative and approaches disclosed herein can further extend to a Galois field having any other size less than or greater than four (for example, a Galois field of size eight or sixteen).

At state transition 1, the variable nodes 210A, 210B, 210C can each output a vector including four LLR values to a respective one of permutation nodes 220A, 220B, 220C. The permutation nodes 220A, 220B, 220C can permute the received vectors including the four LLR values using a corresponding element of a decoding matrix H. At state transition 2, the permutation nodes 220A, 220B, 220C can output the permuted vectors to a respective one of the conversion nodes 230A, 230B, 230C. The permuted vectors can have the form of [LLR₀₀ ^((p) ^(j) ⁾, LLR₀₁ ^((p) ^(j) ⁾, LLR₁₀ ^((p) ^(j) ⁾, LLR₁₁ ^((p) ^(j) ⁾], where j can correspond to the number of a particular node of the permutation nodes 220A, 220B, 220C that outputs the vector, and LLR₀₀ ^((p) ^(j) ⁾, LLR₀₁ ^((p) ^(j) ⁾, LLR₁₀ ^((p) ^(j) ⁾, LLR₁₁ ^((p) ^(j) ⁾ can correspond to the four LLR values of the permuted vector.

The conversion nodes 230A, 230B, 230C can convert the permuted vectors in accordance with a decomposition algorithm to form binary inputs for the binary check nodes 240A, 240B, 240C. For example, each of the conversion nodes 230A, 230B, 230C can convert the permuted vectors according to Equations (1), (2), and (3). L ₀₁ ^((p) ^(j) ⁾=max*(LLR₀₀ ^((p) ^(j) ⁾,LLR₀₁ ^((p) ^(j) ⁾)−max*(LLR₁₀ ^((p) ^(j) ⁾,LLR₁₁ ^((p) ^(j) ⁾)  (1) L ₁₀ ^((p) ^(j) ⁾=max*(LLR₀₀ ^((p) ^(j) ⁾,LLR₁₀ ^((p) ^(j) ⁾)−max*(LLR₀₁ ^((p) ^(j) ⁾,LLR₁₁ ^((p) ^(j) ⁾)  (2) L ₁₁ ^((p) ^(j) ⁾=max*(LLR₀₀ ^((p) ^(j) ⁾,LLR₁₁ ^((p) ^(j) ⁾)−max*(LLR₀₁ ^((p) ^(j) ⁾,LLR₁₀ ^((p) ^(j) ⁾)  (3) where max*(a,b)=max(a,b)+log(1+e^(−|a−b|)); L₀₁ ^((p) ^(j) ⁾ can correspond to the combined message from the subgroup {00,01} and the binary value output from each of the conversion nodes 230A, 230B, 230C to the binary check node 240A; L₁₀ ^((p) ^(j) ⁾ can correspond to the combined message from the subgroup {00,10} and the binary value output from each of the conversion nodes 230A, 230B, 230C to the binary check node 240B; L₁₁ ^((p) ^(j) ⁾ can correspond to the combined message from the subgroup {00,11} and the binary value output from each of the conversion nodes 230A, 230B, 230C to the binary check node 240C. It can be noted that Gs={{00,01},{00,10},{00,11}} and that {00,01},{00,10}, and {00,11} can be the subgroups having a size of two in GF(4).

In some embodiments, the computation for max*(a,b) can be performed using one or more simplifications or approximations. For instance, the computation can be performed using a lookup table or an approximation max*(a,b)≈γ·max(a,b) in place of performing the logarithmic or exponential operations that may otherwise be performed. The value for γ can be selected based on a code rate for the encoded data and set at manufacture of the data storage system 120. The value for γ can be a real number such as 0.75 in one implementation, or more or less in other implementations (for example, such as 0.65, 0.80, 1.00). In certain embodiments, the value for γ may not be based on noise detected on one or more read channels at run-time.

At state transition 3, the conversion nodes 230A, 230B, 230C can each output three binary values for processing by the binary check nodes 240A, 240B, 240C. The binary check nodes 240A, 240B, 240C can then perform a binary check node algorithm to determine a value for output to the inverse conversion node 250. In one example, each of the binary check nodes 240A, 240B, 240C can perform the binary check node algorithm of Equation (4).

$\begin{matrix} {L_{i}^{(c_{m})} = {2\;{{atanh}\left( {\prod\limits_{j}\;{\tanh\left( \frac{L_{i}^{(p_{j})}}{2} \right)}} \right)}}} & (4) \end{matrix}$ where i can correspond to the subgroup for a given binary check node (such as 01, 10, and 11); L_(i) ^((c) ^(m) ⁾ can correspond to the output value for the given binary check node; and m can correspond to the number of a particular node of the binary check nodes 240A, 240B, 240C that outputs the value. In particular, the binary check nodes 240A, 240B, 240C can respectively perform the binary check node algorithms of Equations (5), (6), and (7).

$\begin{matrix} {L_{0\; 1}^{(c_{1})} = {2{{atanh}\left( {\prod\limits_{j}{\tanh\left( \frac{L_{01}^{(p_{j})}}{2} \right)}} \right)}}} & (5) \end{matrix}$

$\begin{matrix} {L_{10}^{(c_{2})} = {2{{atanh}\left( {\prod\limits_{j}{\tanh\left( \frac{L_{10}^{(p_{j})}}{2} \right)}} \right)}}} & (6) \end{matrix}$

$\begin{matrix} {L_{11}^{(c_{3})} = {2{{atanh}\left( {\prod\limits_{j}{\tanh\left( \frac{L_{11}^{(p_{j})}}{2} \right)}} \right)}}} & (7) \end{matrix}$

In another example, each of the binary check nodes 240A, 240B, 240C can perform the binary check node algorithm of Equation (8), which can reduce the memory usage and calculation complexity for performing the binary check node algorithm and enable faster processing and parallelization of performance of some processing by one or more of the conversion nodes 230A, 230B, 230C and the permutation nodes 220A, 220B, 220C.

$\begin{matrix} {L_{i}^{(c_{m})} = {\alpha \cdot \left( {\prod\limits_{j}{{sign}\left( L_{i}^{(p_{j})} \right)}} \right) \cdot {\min\left( {L_{i}^{(p_{j})}} \right)}}} & (8) \end{matrix}$ where i can correspond to the subgroup for a given binary check nodes (such as 01, 10, and 11); α can correspond to a configurable constant such as 0.75, or more or less depending on the implementation (for example, 0.65, 0.80, 1.00); sign(L_(i) ^((p) ^(j) ⁾) can correspond to the product of the signs of L_(i) ^((p) ¹ ⁾, L_(i) ^((p) ² ⁾, and L_(i) ^((p) ^(j) ⁾; min(|L_(i) ^((p) ^(j) ⁾|) can correspond to the minimum L_(i) of L_(i) ^((p) ¹ ⁾, L_(i) ^((p) ² ⁾, and L_(i) ^((p) ³ ⁾; L_(i) ^((c) ^(m) ⁾ can correspond to the output value for a given binary check node; and m can correspond to the number of a given node of the binary check nodes 240A, 240B, 240C that outputs the value. In particular, the binary check nodes 240A, 240B, 240C can respectively perform the binary check node algorithms of Equations (9), (10), and (11).

$\begin{matrix} {L_{01}^{(c_{1})} = {\alpha \cdot \left( {\prod\limits_{j}\;{{sign}\left( L_{01}^{(p_{j})} \right)}} \right) \cdot {\min\left( {L_{01}^{(p_{j})}} \right)}}} & (9) \end{matrix}$

$\begin{matrix} {L_{10}^{(c_{2})} = {\alpha \cdot \left( {\prod\limits_{j}\;{{sign}\left( L_{10}^{(p_{j})} \right)}} \right) \cdot {\min\left( {L_{10}^{(p_{j})}} \right)}}} & (10) \end{matrix}$

$\begin{matrix} {L_{11}^{(c_{3})} = {\alpha \cdot \left( {\prod\limits_{j}\;{{sign}\left( L_{11}^{(p_{j})} \right)}} \right) \cdot {\min\left( {L_{11}^{(p_{j})}} \right)}}} & (11) \end{matrix}$

At state transition 4, the binary check nodes 240A, 240B, 240C can output the determined values of L₀₁ ^((c) ¹ ⁾, L₁₀ ^((c) ² ⁾, and L₁₁ ^((c) ³ ⁾ to the inverse conversion node 250. The inverse conversion node 250 can convert the determined values of L₀₁ ^((c) ¹ ⁾, L₁₀ ^((c) ² ⁾, and L₁₁ ^((c) ³ ⁾ using an inverse of the decomposition so as to form non-binary inputs for the inverse permutation node 260. In one example, the inverse conversion node 250 can convert the determined values according to Equations (12), (13), (14), and (15).

$\begin{matrix} {S_{01} = \frac{e^{L_{01}^{(c_{1})}}}{1 + e^{L_{01}^{(c_{1})}}}} & (12) \end{matrix}$

$\begin{matrix} {S_{10} = \frac{e^{L_{10}^{(c_{2})}}}{1 + e^{L_{10}^{(c_{2})}}}} & (13) \end{matrix}$

$\begin{matrix} {S_{11} = \frac{e^{L_{11}^{(c_{3})}}}{1 + e^{L_{11}^{(c_{3})}}}} & (14) \end{matrix}$

$\begin{matrix} {\left\lbrack {{L\; L\; R_{00}^{(p)}},{L\; L\; R_{01}^{(p)}},{L\; L\; R_{10}^{(p)}},{L\; L\; R_{11}^{(p)}}} \right\rbrack = \left\lbrack {0,{\log\left( \frac{S_{01} - S_{10} - S_{11} + 1}{S_{01} + S_{10} + S_{11} - 1} \right)},{\log\left( \frac{S_{10} - S_{01} - S_{11} + 1}{S_{01} + S_{10} + S_{11} - 1} \right)},{\log\left( \frac{S_{11} - S_{01} - S_{10} + 1}{S_{01} + S_{10} + S_{11} - 1} \right)}} \right\rbrack} & (15) \end{matrix}$ where S₀₁, S₁₀, and S₁₁ can correspond to intermediate values used to determine the values for the vector [LLR₀₀ ^((p)), LLR₀₁ ^((p)), LLR₁₀ ^((p)), LLR₁₁ ^((p))] output from the inverse conversion node 250.

In another example, the determined values of L₀₁ ^((c) ¹ ⁾, L₁₀ ^((c) ² ⁾, and L₁₁ ^((c) ³ ⁾ can instead be sorted and compared with zero, and based on the result of the comparison, the values for the vector [LLR₀₀ ^((p)), LLR₀₁ ^((p)), LLR₁₀ ^((p)), LLR₁₁ ^((p))] can be determined by using an approximation sort algorithm. The approximation sort algorithm can include assigning 0 to the largest element, the second largest of the determined values to the second largest element, the third largest of the determined values to the third largest element, and β times the sum of the second and third largest determined values to the fourth largest element. For instance, assuming L₀₁ ^((c) ^(m) ⁾<L₁₀ ^((c) ^(m) ⁾<0<L₁₁ ^((c) ^(m) ⁾, the values for the vector [LLR₀₀ ^((p)), LLR₀₁ ^((p)), LLR₁₀ ^((p)), LLR₁₁ ^((p))] can be determined according to Equation (16). [LLR₀₀ ^((p)),LLR₀₁ ^((p)),LLR₁₀ ^((p)),LLR₁₁ ^((p)) ]=[−|L ₀₁ ^((c) ^(m) ⁾|,β(−|L ₁₁ ^((c) ^(m) ⁾ |−|L ₀₁ ^((c) ^(m) ⁾|),−|L ₁₁ ^((c) ^(m) ⁾|,0]  (16)

At state transition 5, the inverse conversion node 250 can output the determined vector [LLR₀₀ ^((p)), LLR₀₁ ^((p)), LLR₁₀ ^((p)), LLR₁₁ ^((p))] to the inverse permutation node 260. The inverse permutation node 260 can inversely permute the determined vector [LLR₀₀ ^((p)), LLR₀₁ ^((p)), LLR₁₀ ^((p)), LLR₁₁ ^((p))] using a corresponding element of the decoding matrix H before outputting the results of the inverse permutation to the variable nodes 210A, 210B, 210C at state transition 6. The variable nodes 210A, 210B, 210C can perform a summation of the received LLR values of the inversely permuted vectors and make a decision.

FIGS. 3A and 3B illustrate a flow diagram 300 depicting algorithms and data transfers in a LDPC decoding process by a decoder, such as the decoder module 132 or the decoder 156. The flow diagram 300 can illustrate a first decoder implementation of algorithms and data transfers in the LDPC decoding process illustrated in the flow diagram 200. Advantageously, the flow diagram 300 provides algorithms for the conversion nodes 230A, 230B, 230C, the binary check nodes 240A, 240B, 240C, and the inverse conversion node 250 that can, in combination, enable the nodes to arrive at the same decoding results as if the nodes formed a non-binary check node.

In a second decoder implementation of algorithms and data transfers in the LDPC decoding process illustrated in the flow diagram 200, the decoder can implement the decoding process of the flow diagram 300, with the exception of using the approximation algorithms of Equations (9), (10), and (11) to respectively perform the check node updates at the binary check nodes 240A, 240B, 240C.

In a third decoder implementation of algorithms and data transfers in the LDPC decoding process illustrated in the flow diagram 200, the decoder can implement the decoding process of the flow diagram 300, with the exception of: (i) using the approximation algorithms of Equations (9), (10), and (11) to respectively perform the check node updates at the binary check nodes 240A, 240B, 240C, (ii) using the approximation algorithm of max*(a,b)≈γ·max(a,b) to solve for max*(a,b) at the conversion nodes 230A, 230B, 230C, and (iii) using an approximation sort algorithm, such as illustrated with respect to Equation (16), to solve for the values of the vector [LLR₀₀ ^((p)), LLR₀₁ ^((p)), LLR₁₀ ^((p)), LLR₁₁ ^((p))] at the inverse conversion node 250.

FIGS. 4 and 5 are graphs 400 and 500 illustrating signal-to-noise ratios for given page error rates for example decoders, such as the decoder module 132 or the decoder 156. Table 1 below provides a legend for relating the graph labels in the graph 400 and the corresponding decoder implementations described herein.

TABLE 1 Graph Label Disclosure Implementation 410 traditional non-binary LDPC decoder 408 first decoder implementation 406 second decoder implementation: α = 0.65 404 second decoder implementation: α = 0.70 402 second decoder implementation: α = 0.60 Table 2 below provides a legend for relating the graph labels in the graph 500 and the corresponding decoder implementations described herein.

TABLE 2 Graph Label Disclosure Implementation 508 traditional non-binary LDPC decoder 506 first decoder implementation 504 third decoder implementation: α = 0.75, β = 0.75, γ = 1.0 502 second decoder implementation: α = 0.65

As can be seen from the graphs 400 and 500, the performance of the first decoder implementation can match the performance of the traditional non-binary LDPC decoder. In addition, the performance loss from using the second or third decoder implementations can be relatively small compared to using the traditional non-binary LDPC decoder and first decoder implementation, especially for relatively higher signal-to-noise ratios.

FIG. 6 illustrates a decoding process 600 performable by a decoder, such as the decoder module 132 or the decoder 156. For convenience, the process 600 is described in the context of the flow diagram 200, but may instead be implemented using other approaches described herein or other computing approaches not shown. The process 600 provides one example way by which a LDPC decoder can perform non-binary decoding of an LDPC encoded data unit using binary processing. In particular, the process 600 demonstrates how check nodes of a LDPC decoder can be used to process binary values while other nodes (such as variable or permutation nodes) of a LDPC decoder can be used to process non-binary values.

At block 602, the conversion nodes 230A, 230B, 230C can convert input non-binary values to input binary values in accordance with a decomposition algorithm. The input non-binary values can be permuted vectors including LLR values determined based on an LDPC encoded data unit or from a previous decoding iteration. In one example, each of the conversion nodes 230A, 230B, 230C can convert the permuted vectors according to Equations (1), (2), and (3).

At block 604, the binary check nodes 240A, 240B, 240C can perform a binary check node algorithm to determine output binary values from the input binary values. For instance, the binary check nodes 240A, 240B, 240C can respectively perform the binary check node algorithms of Equations (5), (6), and (7).

At block 606, the inverse conversion node 250 can convert the output binary values to output non-binary values in accordance with an inverse decomposition algorithm. The inverse decomposition algorithm can be an inverse algorithm from the decomposition algorithm of block 602. For example, the inverse conversion node 250 can convert the output binary values according to Equations (12), (13), (14), and (15).

Other Variations

Although some embodiments of this disclosure may have been described using data storage systems or controllers for non-volatile storage media as examples, the disclosure can further apply to other environments and applications where data coding may be utilized. For example, the disclosure can apply to technologies where a non-binary LDPC signal can be read from a channel or data source (for example, the data communication channel 154) and then decoded using one or more binary decoders (for example, the decoder 156). In one such example, the disclosure can be used for decoding one or more communication channels in a telecommunications system, for instance, such as a mobile communications system or wireless communications system. Moreover, in some embodiments, statistical or probability metrics can be used in addition to or instead of log likelihood ratios.

The actual steps taken in the disclosed processes, such as the process 600 illustrated in FIG. 6, may differ from those shown herein. Additional system components can further be utilized, and disclosed system components can be combined or omitted. Depending on the embodiment, certain of the steps described above may be removed, others may be added.

Although the flow diagrams and approaches herein may be described in terms of outputting and receiving reliability values, for example, it should be understood that the output and received reliability values may actually be reliability information representing the reliability values output or received. For instance, reliability information itself can include one or more “0” or “1” values that may have no specific meaning when standing alone. However, when understood in a particular context, the one or more “0” or “1” values of the reliability information can represent a particular binary or non-binary value, for example, that may be output or received.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the protection. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the protection. For example, the various components illustrated in the figures may be implemented as software and/or firmware on a processor, ASIC/FPGA, or dedicated hardware. Hardware components, such as processors, ASICs, FPGAs, and the like, can include logic circuitry. Also, the features and attributes of the specific embodiments disclosed above may be combined in different ways to form additional embodiments, all of which fall within the scope of the present disclosure. Although the present disclosure provides certain preferred embodiments and applications, other embodiments that are apparent to those of ordinary skill in the art, including embodiments which do not provide all of the features and advantages set forth herein, are also within the scope of this disclosure. 

What is claimed is:
 1. An electronic system, comprising: a decoder configured to decode at least one encoded data unit of a plurality of encoded data units using a plurality of variable nodes and a plurality of check nodes to perform a low-density parity check (LDPC) decoding process, the plurality of encoded data units provided by a data source, wherein, as part of performing the LDPC decoding process, the decoder is configured to: convert reliability information representing a first plurality of non-binary values to reliability information representing a first plurality of binary values, the reliability information representing the first plurality of binary values being sent to the plurality of check nodes in a plurality of first messages, determine reliability information representing a second plurality of binary values, the reliability information representing the second plurality of binary values being determined based on the reliability information representing the first plurality of binary values, and convert the reliability information representing the second plurality of binary values to reliability information representing a second plurality of non-binary values, the reliability information representing the second plurality of non-binary values being sent to the plurality of variable nodes in a plurality of second messages.
 2. The electronic system of claim 1, wherein the plurality of variable nodes is configured to process reliability information representing non-binary parameters as part of the LDPC decoding process, and the plurality of check nodes is configured to process reliability information representing binary parameters as part of the LDPC decoding process.
 3. The electronic system of claim 1, wherein the decoder is further configured to determine the reliability information representing the second plurality of binary values by performing one or more check node updates using the plurality of check nodes.
 4. The electronic system of claim 1, wherein the decoder is further configured to: convert the reliability information representing the first plurality of non-binary values to the reliability information representing the first plurality of binary values in accordance with a decomposition; and convert the reliability information representing the second plurality of binary values to the reliability information representing the second plurality of non-binary values in accordance with an inverse decomposition.
 5. The electronic system of claim 1, wherein the decoder is further configured to convert the reliability information representing the first plurality of non-binary values to the reliability information representing the first plurality of binary values without performing logarithmic or exponential computations.
 6. The electronic system of claim 1, wherein the decoder is further configured to convert the reliability information representing the second plurality of binary values to the reliability information representing the second plurality of non-binary values without performing logarithmic or exponential computations.
 7. The electronic system of claim 1, wherein the decoder is further configured to decode the at least one encoded data unit using the plurality of check nodes without performing hyperbolic or inverse hyperbolic computations.
 8. The electronic system of claim 1, wherein the decoder is further configured to convert the reliability information representing the first plurality of non-binary values to reliability information representing one of the first plurality of binary values in accordance with: L ₀₁=max(LLR₀₀,LLR₀₁)+log(1+e ^(−|LLR) ⁰⁰ ^(−LLR) ⁰¹ ^(|))−(max(LLR₁₀,LLR₁₁)+log(1+e ^(−|LLR) ¹⁰ ^(−LLR) ¹¹ ^(|))) where L₀₁ comprises the one of the first plurality of binary values, and LLR₀₀, LLR₀₁, LLR₁₀, and LLR₁₁ comprise at least some of the first plurality of non-binary values.
 9. The electronic system of claim 1, wherein the decoder is further configured to convert the reliability information representing the first plurality of non-binary values to reliability information representing one of the first plurality of binary values in accordance with: L ₀₁γ·max(LLR₀₀,LLR₀₁)−γ·max(LLR₁₀,LLR₁₁) where L₀₁ comprises the one of the first plurality of binary values, LLR₀₀, LLR₀₁, LLR₁₀, and LLR₁₁ comprise at least some of the first plurality of non-binary values, and γ comprises a real number.
 10. The electronic system of claim 1, wherein the decoder is further configured to convert the reliability information representing the second plurality of binary values to the reliability information representing the second plurality of non-binary values in accordance with: $\left\lbrack {{L\; L\; R_{00}},{L\; L\; R_{01}},{L\; L\; R_{10}},{L\; L\; R_{11}}} \right\rbrack = \left\lbrack {0,{\log\left( \frac{S_{01} - S_{10} - S_{11} + 1}{S_{01} + S_{10} + S_{11} - 1} \right)},{\log\left( \frac{S_{10} - S_{01} - S_{11} + 1}{S_{01} + S_{10} + S_{11} - 1} \right)},{\log\left( \frac{S_{11} - S_{01} - S_{10} + 1}{S_{01} + S_{10} + S_{11} - 1} \right)}} \right\rbrack$ where ${S_{01} = \frac{e^{L_{01}}}{1 + e^{L_{01}}}},{S_{10} = \frac{e^{L_{10}}}{1 + e^{L_{10}}}},{S_{11} = \frac{e^{L_{11}}}{1 + e^{L_{11}}}},$ and LLR₀₀, LLR₀₁, LLR₁₀, and LLR₁₁ comprise at least some of the second plurality of non-binary values, and L₀₁, L₁₀, and L₁₁ comprise at least some of the second plurality of binary values.
 11. The electronic system of claim 1, wherein the first plurality of non-binary values and the second plurality of non-binary values comprise log-likelihood ratio (LLR) values.
 12. The electronic system of claim 1, wherein, as part of performing the LDPC decoding process, the decoder is further configured to: permute the reliability information representing the first plurality of non-binary values before converting the reliability information representing the first plurality of non-binary values to the reliability information representing the first plurality of binary values; and inversely permute the reliability information representing the second plurality of non-binary values after converting the reliability information representing the second plurality of binary values to the reliability information representing the second plurality of non-binary values.
 13. The electronic system of claim 1, wherein the data source comprises a solid-state memory array configured to store the plurality of encoded data units, and the plurality of encoded data units comprises information representing non-binary parameters and data received from a host system.
 14. The electronic system of claim 13, wherein the solid-state memory array comprises multi-level cell (MLC) NAND memory.
 15. A data storage system, comprising: a solid-state memory array configured to store a plurality of encoded data units; and a controller configured to receive at least one encoded data unit of the plurality of encoded data units from the solid-state memory array and decode the at least one encoded data unit using a plurality of variable nodes and a plurality of check nodes to perform a low-density parity check (LDPC) decoding process, wherein, as part of performing the LDPC decoding process, the controller is configured to: convert reliability information representing a first plurality of non-binary values to reliability information representing a first plurality of binary values, the reliability information representing the first plurality of binary values being sent to the plurality of check nodes in a plurality of first messages, determine reliability information representing a second plurality of binary values, the reliability information representing the second plurality of binary values being determined based on the reliability information representing the first plurality of binary values, and convert the reliability information representing the second plurality of binary values to reliability information representing a second plurality of non-binary values, the reliability information representing the second plurality of non-binary values being sent to the plurality of variable nodes in a plurality of second messages.
 16. The data storage system of claim 15, wherein the plurality of variable nodes are configured to process reliability information representing non-binary parameters as part of the LDPC decoding process, and the plurality of check nodes are configured to process reliability information representing binary parameters as part of the LDPC decoding process.
 17. The data storage system of claim 15, wherein the decoder is further configured to convert the reliability information representing the first plurality of non-binary values to the reliability information representing the first plurality of binary values without performing logarithmic or exponential computations.
 18. The data storage system of claim 15, wherein, as part of performing the LDPC decoding process, the controller is further configured to: permute the reliability information representing the first plurality of non-binary values before converting the reliability information representing the first plurality of non-binary values to the reliability information representing the first plurality of binary values; and inversely permute the reliability information representing the second plurality of non-binary values after converting the reliability information representing the second plurality of binary values to the reliability information representing the second plurality of non-binary values.
 19. A method for decoding data, comprising: decoding at least one encoded data unit of a plurality of encoded data units using a plurality of variable nodes and a plurality of check nodes to perform a low-density parity check (LDPC) decoding process, the plurality of encoded data units retrieved from a solid-state memory array configured to store the plurality of encoded data units, wherein said decoding comprises: converting reliability information representing a first plurality of non-binary values to reliability information representing a first plurality of binary values, the reliability information representing the first plurality of binary values being sent to the plurality of check nodes in a plurality of first messages, determining reliability information representing a second plurality of binary values, the reliability information representing the second plurality of binary values being determined based on the reliability information representing the first plurality of binary values, and converting the reliability information representing the second plurality of binary values to reliability information representing a second plurality of non-binary values, the reliability information representing the second plurality of non-binary values being sent to the plurality of variable nodes in a plurality of second messages, wherein the method is performed by a decoder comprising computer hardware.
 20. The method of claim 19, wherein said decoding further comprises: permuting the reliability information representing the first plurality of non-binary values before converting the reliability information representing the first plurality of non-binary values to the reliability information representing the first plurality of binary values; and inversely permuting the reliability information representing the second plurality of non-binary values after converting the reliability information representing the second plurality of binary values to the reliability information representing the second plurality of non-binary values. 